Integrated circuit provided with a protection against electrostatic discharges

ABSTRACT

An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of French patentapplication number 10/50860, filed on Feb. 8, 2010, entitled “IntegratedCircuit Provided with a Protection Against Electrostatic Discharges,”which is hereby incorporated by reference to the maximum extentallowable by law.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the protection of integrated circuitsagainst electrostatic discharges.

2. Discussion of the Related Art

An integrated circuit comprises metal pads intended to provideconnections to the outside. Some of the pads are capable of receivingpower supply voltages. The other pads are capable of receiving and/or ofproviding input/output signals. Power supply rails, connected to thesupply pads, are generally provided all around the circuit to power itsdifferent components. Generally, an insulating layer covers the circuit,only leaving access to the metal pads.

Such a circuit generally receives and/or delivers signals of low voltagelevel (for example, from 1 to 5 V) and of low current intensity (forexample, from 1 μA to 10 mA), and may be damaged when overvoltages oroverintensities occur between pads of the circuit.

It is thus provided to associate a protection structure with each pad.The protection structure should be able to rapidly drain off significantcurrents, that appear when an electrostatic discharge occurs on aninput/output pad (“pad”, for simplification) or on a pad connected to apower supply rail (“rail”, for simplification).

FIG. 1 shows an example of a protection structure 1 associated with anintegrated circuit input/output pad 3. A diode 5 is forward connectedbetween pad 3 and a high power supply rail V_(DD). A diode 7 isreverse-connected between pad 3 and a low power supply rail V_(SS). AMOS transistor 9, used as a switch, is connected between high and lowpower supply rails V_(DD) and V_(SS). An overvoltage detection circuit11, connected in parallel with MOS transistor 9, provides a triggersignal to this transistor. MOS transistor 9 comprises a parasitic diode10, forward connected between rail V_(SS) and rail V_(DD).

In normal operation, when the chip is powered, the signals on pad 3 andrails V_(DD) and V_(SS) are such that diodes 5 and 7 conduct no currentand detection circuit 11 makes MOS transistor 9 non-conductive.

In case of a positive overvoltage between rails V_(DD) and V_(SS),circuit 11 turns on transistor 9, which enables to remove theovervoltage.

In case of a negative overvoltage between rails V_(DD) and V_(SS),parasitic diode 10 of transistor 9 becomes conductive and theovervoltage is removed.

In case of a positive overvoltage between pad 3 and high power supplyrail V_(DD), diode 5 becomes conductive and the overvoltage is removed.

In case of a negative overvoltage between pad 3 and rail V_(DD), circuit11 turns on transistor 9 and the overvoltage is removed throughtransistor 9 and diode 7.

In case of a positive overvoltage between pad 3 and rail V_(SS), diode 5becomes conductive and the positive overvoltage is transferred onto railV_(DD), which corresponds to the above case of a positive overvoltagebetween rails V_(DD) and V_(SS).

In case of a negative overvoltage between pad 3 and rail V_(SS), diode 7becomes conductive and the overvoltage is removed.

In case of a positive or negative overvoltage between two input/outputpads 3, diodes 5 or 7 associated with the concerned pads becomeconductive, and the overvoltage is transferred onto high and low powersupply rails V_(DD) and V_(SS). This corresponds to one of the aboveovervoltage cases.

FIG. 2 partly shows the diagram of FIG. 1 and shows in further detail anexample of a possible embodiment of a circuit 11 for detecting apositive overvoltage between rails V_(DD) and V_(SS), and forcontrolling protection transistor 9. An edge detector, formed of aresistor 21 in series with a capacitor 23, is connected between powersupply rails V_(DD) and V_(SS). Node M between resistor 21 and capacitor23 is connected to the gate of a P-channel MOS transistor 25 having itssource connected to rail V_(DD) and having its drain connected to railV_(SS) via a resistor 27. Node N between the drain of transistor 25 andresistor 27 is connected to the gate of transistor 9. An assembly 29 ofdiodes in series is forward-connected between node M and rail V_(SS). Inthis example, assembly 29 comprises four diodes in series.

In normal operation, when the circuit is powered, node M is in a highstate. P-channel MOS transistor 25 thus conducts no current. Thus, gatenode N of transistor 9 is in a low state, and protection transistor 9 ismaintained off. When the potential difference between rails V_(DD) andV_(SS) increases, the voltage of node M also increases. When the voltageof node M reaches a given threshold, diode assembly 29 becomesconductive. In this example, if each diode has a 0.6-V thresholdvoltage, assembly 29 becomes conductive when the voltage of node Mexceeds 2.4 V. This results in a voltage drop at node M, which turns onP-channel MOS transistor 25. Thus, gate node N of protection transistor9 switches to a high state, that is, substantially to the same positivevoltage as rail V_(DD). Transistor 9 thus becomes conductive and theovervoltage is removed.

When the integrated circuit is not powered, node M is in a low state.Since transistor 25 is not powered, drain node N of this transistor isin an undetermined state. If an abrupt positive overvoltage (fastvoltage rise) occurs between rails V_(DD) and V_(SS), node M remains ina low state. Transistor 25 thus becomes conductive and node N switchesto a high state. Thus, protection transistor 9 is made conductive andthe overvoltage is removed.

A disadvantage of the protection structure of FIGS. 1 and 2 lies in thefact that, to be able to drain off the currents induced by electrostaticdischarges, diodes 5 and 7 and transistor 9 should have a large surfacearea (for example, a 200-μm junction perimeter per diode and a channelwidth of several tens of millimeters for the transistor). As a result, asignificant silicon surface area is exclusively dedicated to theprotection against electrostatic discharges, to the detriment of theother circuit components. Further, due to its large size, MOS transistor9, in the off state, is crossed by significant leakage currents, whichincreases the circuit power consumption and the stray capacitancebetween rails V_(DD) and V_(SS).

SUMMARY OF THE INVENTION

An object at least one embodiment of the present invention is to providean integrated circuit provided with a protection against electrostaticdischarges, where this protection does not increase the silicon surfacearea taken up by the same circuit when unprotected or only slightly doesso.

An object of an embodiment of the present invention is to provide such aprotection which does not disturb the proper operation of the circuit innormal conditions of use.

An object of an embodiment of the present invention is to provide such aprotection which is easy to implement.

An embodiment of the present invention provides using, in case of anovervoltage, MOS power transistors, existing in the output amplificationstages of the integrated circuit, as an overvoltage removal path.

Thus, an embodiment of the present invention provides an integratedcircuit protected against electrostatic discharges, having output padscoupled to amplification stages, each stage comprising, between firstand second power supply rails, a P-channel MOS power transistor inseries with an N-channel MOS power transistor, this integrated circuitfurther comprising protection means for simultaneously turning on thetwo transistors when a positive overvoltage occurs between the first andsecond power supply rails.

According to an embodiment of the present invention, in eachamplification stage, the sources of the P- and N-channel transistors arerespectively connected to the first and second power supply rails, andthe drains of the transistors are connected to the output pad.

According to an embodiment of the present invention, the integratedcircuit comprises a control circuit for each amplification stage tocontrol, in normal operation, the turning off and the turning on of thetransistors, this control circuit comprising at least one outputconnected to the gates of the P-channel and N-channel transistors, andthe protection means comprise: first and second resistors respectivelyconnected between the output of the control circuit and the respectivegates of the P-channel and N-channel transistors; and a detection andtrigger circuit comprising first and second outputs respectivelyconnected to the gates of the P-channel and N-channel transistors,capable of simultaneously turning on the two transistors when a positiveovervoltage occurs between the first and second power supply rails.

According to an embodiment of the present invention, the amplificationstage control circuit is connected to the first and second power supplyrails via P-channel and N-channel MOS transistors, having theirrespective gates connected to edge detectors capable of controlling theturning off of these transistors when a positive overvoltage occursbetween the first and second power supply rails.

According to an embodiment of the present invention, the detection andtrigger circuit comprises: a first zener diode forward-connected betweenits second output and the first rail; and a second zener diodeforward-connected between the second rail and its first output.

According to an embodiment of the present invention, the detection andtrigger circuit comprises: a first edge detector comprising a resistorin series with a capacitor, connected between the first and secondrails; a second edge detector comprising a resistor in series with acapacitor, connected between the second and first rails; a P-channel MOStransistor having its source and its drain respectively connected to thefirst rail and to the first output, and having its gate connectedbetween the resistor and the capacitor of the first edge detector; anN-channel MOS transistor having its source and its drain respectivelyconnected to the second rail and to the second output, and having itsgate connected between the resistor and the capacitor of the second edgedetector; and first and second zener diodes respectivelyforward-connected between the second rail and the gate of the P-channeltransistor, and between the gate of the N-channel transistor and thefirst rail.

The foregoing objects, features, and advantages of the present inventionwill be discussed in detail in the following non-limiting description ofspecific embodiments in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1, previously described, shows an example of a structure ofprotection against overvoltages associated with a pad of an integratedcircuit;

FIG. 2, previously described, partly shows the diagram of FIG. 1, andshows in further detail a possible embodiment of a detector of apositive overvoltage between the power supply rails of the integratedcircuit;

FIG. 3 shows the diagram of FIG. 1, and further shows an amplificationstage, associated with an output pad of an integrated circuit;

FIG. 4 partly shows the diagram of FIG. 3 and shows in further detail apossible embodiment of an output amplification stage of an integratedcircuit;

FIG. 5 shows a structure of protection against overvoltages using, as aprotection element, the transistors of an output amplification stage ofan integrated circuit;

FIG. 6 shows in further detail an embodiment of the protection structureof FIG. 5;

FIG. 7 shows an embodiment of a detection and trigger circuit associatedwith a protection structure of the type described in relation with FIG.6;

FIG. 8 shows another embodiment of a detection and trigger circuitassociated with a protection structure of the type described in relationwith FIG. 6;

FIG. 9 shows an alternative embodiment of a protection structure of thetype described in relation with FIGS. 5 and 6;

FIG. 10 shows an embodiment of a detection and trigger circuitassociated with a protection structure of the type described in relationwith FIG. 9; and

FIG. 11 shows another embodiment of a detection and trigger circuitassociated with a protection structure of the type described in relationwith FIG. 9.

DETAILED DESCRIPTION

For clarity, the same elements have been designated with the samereference numerals in the different drawings.

In an integrated circuit, an output amplification stage is associatedwith each output pad, to adapt the (low) power of the internal signalsof the circuit, to a (higher) level exploitable outside of the circuit.

FIG. 3 shows the diagram of FIG. 1 of a protection structure associatedwith a pad 3 of an integrated circuit, in the case where this pad is anoutput pad. In this case, an output amplification stage is associatedwith pad 3.

The output amplification stage comprises a P-channel MOS powertransistor 31, in series with an N-channel MOS power transistor 33. Thesources of transistors 31 and 33 are respectively connected to high andlow power supply rails V_(DD) and V_(SS). The drains of transistors 31and 33 are interconnected at a node connected to output pad 3 of thecircuit. A control circuit 35 of the amplification stage is provided tocontrol the gates of transistors 31 and 33. In this example, circuit 35comprises two inputs IN and LOW-Z, and two outputs, respectivelyconnected to the gates of transistors 31 and 33, to control the flowingof the current in one or the other of transistors 31 and 33 according tothe state of inputs IN and LOW-Z. Signal IN corresponds to the signalwhich should be amplified by the amplification stage. Signal LOW-Zcontrols the setting of the output pad to high impedance, that is, thesimultaneous turning off of transistors 31 and 33. For its power supply,circuit 35 is connected to rails V_(DD) and V_(SS).

FIG. 4 shows in further detail a possible embodiment of circuit 35 forcontrolling output amplification stage 31, 33. Circuit 35 comprises athree-input NAND gate 41 and a three-input NOR gate 43. The outputs ofNAND gate 41 and NOR gate 43 are respectively connected to the gates oftransistors 31 and 33. NAND gate 41 receives signal IN, signal LOW-Z,and the output signal of NOR gate 43 inverted by an inverter 45. NORgate 43 receives signal IN, signal LOW-Z inverted by an inverter 46, andthe output signal of NAND gate 41 inverted by an inverter 47. For theirpower supply, logic gates 41, 43, 45, 46, and 47 are connected to powersupply rails V_(DD) and V_(SS).

When signal LOW-Z is in a low state, to set output pad 3 to highimpedance, the gate nodes of transistors 31 and 33 are respectively inhigh and low states. Thus, transistors 31 and 33 are both off, and pad 3is at high impedance.

When signal LOW-Z is in a low state, the state of the gate nodes oftransistors 31 and 33 is determined by signal IN.

Control circuit 35 is provided to control the turning-on of one or theother of transistors 31 and 33 (amplification of input signal IN) or thesimultaneous turning-off of transistors 31 and 33 (setting to highimpedance of the output pad), but never the simultaneous turning-on oftwo transistors, which would short-circuit the integrated circuit powersupply. The return of the output signal of NAND gate 41 to the input ofNOR gate 43, via inverter 47, and the return of the output signal of NORgate 43 to the input of NAND gate 41, via inverter 45, enable toascertain that power transistors 31 and 33 are not simultaneously on,even for a short time, for example, in switchings of signal IN.

It is here provided to use the MOS power transistors of the outputamplification stage of an integrated circuit as an electrostaticdischarge removal path. It is especially provided, in case of a positiveovervoltage between power supply rails V_(DD) and V_(SS), tosimultaneously turn on transistors 31 and 33 to enable to remove theovervoltage.

FIG. 5 schematically shows an embodiment of a protection structureassociated with an output pad of an integrated circuit, using thetransistors of the output amplification stage associated with the pad aselements of protection against electrostatic discharges.

A control circuit 51, connected between power supply rails V_(DD) andV_(SS), is provided to control the gates of transistors 31 and 33 of theoutput amplification stage associated with pad 3. Parasitic diodes 32and 34 of transistors 31 and 33 have been shown in the drawing. Diodes32 and 34 are respectively forward-connected between pad 3 and railV_(DD) and reverse-connected between pad 3 and rail V_(SS). Like controlcircuit 35 described in relation with FIGS. 3 and 4, circuit 51comprises two inputs IN and LOW-Z, and two outputs, respectivelyconnected to the gates of transistors 31 and 33, to control the flowingof the current in one or the other of the transistors according to thestate of inputs IN and LOW-Z. Circuit 51 further comprises protectionmeans for controlling the simultaneous turning-on of transistors 31 and33 in case of a positive overvoltage between rails V_(DD) and V_(SS).

In case of a positive overvoltage between rails V_(DD) and V_(SS),circuit 51 controls the turning-on of transistors 31 and 33, whichenables to remove the overvoltage.

In case of a negative overvoltage between rails V_(DD) and V_(SS),diodes 34 and 32 become conductive and the overvoltage is removed.

In case of a positive overvoltage between pad 3 and high power supplyrail V_(DD), diode 32 becomes conductive and the overvoltage is removed.

In case of a negative overvoltage between pad 3 and rail V_(DD), circuit51 controls the turning-on of transistors 31 and 33 and the overvoltageis removed through transistor 31.

In case of a positive overvoltage between pad 3 and rail V_(SS), diode32 becomes conductive and the positive overvoltage is transferred ontorail V_(DD). Circuit 51 controls the turning-on of transistors 31 and 33and the overvoltage is removed through transistor 33.

In case of a negative overvoltage between pad 3 and rail V_(SS), diode34 becomes conductive and the overvoltage is removed.

In case of a positive or negative overvoltage between two input/outputpads 3, diode 32 associated with the most positive pad becomesconductive. Circuit 51 then controls the turning-on of transistors 31and 33, and the overvoltage is removed via transistor 33 associated withthe most positive pad and via diode 34 associated with the leastpositive pad and, in parallel, via diode 32 associated with the mostpositive pad and via transistor 31 associated with the least positivepad.

Thus, transistors 31 and 33 enable removing any type of overvoltagecapable of occurring between two (output) pads or rails of the circuit.Due to their normal power amplification function, transistors 31 and 33have significant dimensions, and can advantageously replace theprotection elements of conventional structures of the type described inrelation with FIGS. 1 and 2 (transistor 9 and diodes 5 and 7). It shouldbe noted that, to provide a full protection of the circuit, it may beprovided to associate a protection adapted to the input pads of thecircuit, for example, diodes of the type of diodes 5 and 7 of FIG. 1,capable of transferring onto their power supply rails the overvoltageslikely to occur on the input pads. The overvoltages can then be removedvia the output stages of the output pads. FIG. 6 shows the diagram ofFIG. 5, and shows in further detail an embodiment of the circuit forcontrolling the transistors of the output amplification stage (circuit51 of FIG. 5).

Like circuit 35 described in relation with FIG. 4 the circuit of FIG. 6comprises a logic block comprising a NAND gate 41, a NOR gate 43, andinverters 45, 46, and 47, to control, in normal operation, the gates oftransistors 31 and 33 according to the state of input signals IN andLOW-Z.

Resistors 73 and 75 are respectively added between the output of NANDgate 41 and the gate of transistor 31 and between the output of NOR gate43 and the gate of transistor 33.

Further, a detection and trigger circuit 77 is connected between powersupply rails V_(DD) and V_(SS). Circuit 77 comprises outputs CDP andCDN, respectively connected to the gates of transistors 31 and 33.

An edge detector, formed of a capacitor 63 in series with a resistor 65,is connected between rails V_(DD) and V_(SS). NAND gate 41 is connectedto power supply rail V_(DD) via a P-channel MOS transistor 61 having itsgate connected to node A between capacitance 63 and resistor 65. Thesource and the drain of transistor 61 are respectively connected to railV_(DD) and to the high power supply terminal of NAND gate 41. The lowpower supply terminal of NAND gate 41 is connected to rail V_(SS).

Similarly, the power supply of NOR gate 43 is coupled with an edgedetector, formed of a capacitor 69 in series with a resistor 71,connected between rails V_(SS) and V_(DD). NOR gate 43 is connected topower supply rail V_(SS) via an N-channel MOS transistor 67 having itsgate connected to a node B between capacitor 69 and resistor 71. Thesource and the drain of transistor 67 are respectively connected to railV_(SS) and to the low power supply terminal of NOR gate 43. The highpower supply terminal of NOR gate 43 is connected to rail V_(DD).

In normal operation, signals CDP and CDN are at high impedance and donot disturb the operation of the amplification stage control circuit.Further, nodes A and B respectively are in low and high states,maintaining transistors 61 and 67 on. Thus, the circuit for controllingthe amplification stage is powered normally.

In case of a positive overvoltage between rails V_(DD) and V_(SS),signals CDP and CDN respectively switch to low and high states. Thus,due to the presence of resistors 73 and 75, whatever the output state ofNAND gate 41 and NOR gate 43, the voltage on the gate of P-channel MOStransistor 31 is smaller than the voltage of rail V_(DD), and thevoltage on the gate of N-channel MOS transistor 33 is greater than thevoltage of rail V_(SS). This causes the simultaneous turning-on oftransistors 31 and 33 and the removal of the overvoltage.

The coupling of the power supplies of NAND gate 41 and NOR gate 43 withedge detectors is an additional way of ascertain the turning-on oftransistors 31 and 33, when a fast positive overvoltage occurs betweenrails V_(DD) and V_(SS), while the integrated circuit is not powered.When the integrated circuit is not powered, node A between resistor 65and capacitor 63 is in a low state. When a fast overvoltage occursbetween rails V_(DD) and V_(SS), node A immediately switches to a highstate, that is, substantially to the same voltage as rail V_(DD), whichcauses the turning-off of transistor 61. Thus, despite the presence of apositive voltage between rails V_(DD) and V_(SS), NAND gate 41 is notpowered and its output remains floating, in an undetermined state.Output signal CDP of circuit 77 can thus freely control the turning-onof transistor 31 to enable to remove the overvoltage. A substantiallysymmetrical line of argument applies to NOR gate 43 and to transistor33.

FIG. 7 shows an embodiment of detection and trigger circuit 77 of theprotection structure of FIG. 6. This circuit comprises zener diodes 81and 83, respectively forward-connected between output CDN of the circuitand rail V_(DD), and reverse-connected between output CDP of the circuitand rail V_(SS).

In normal operation, when the circuit is powered, diodes 81 and 83 arenon-conductive, and outputs CDN and CDP of the circuit are at highimpedance.

When the potential difference between rails V_(DD) and V_(SS) exceeds agiven threshold, diodes 81 and 83 become conductive in reverse mode, byavalanche effect. Thus, output CDN switches to a high state, that is,substantially at the same voltage as rail V_(DD) minus a value V_(Z)corresponding to the threshold voltage of diode 81. Further, output CDPswitches to a low state, that is, substantially to voltage V_(Z)corresponding to the threshold voltage of diode 83.

FIG. 8 shows a preferred alternative embodiment of detection and triggercircuit 77 of the protection structure of FIG. 6. An edge detector,formed of a resistor 91 in series with a capacitor 93, is connectedbetween power supply rails V_(DD) and V_(SS). Node D between resistor 91and capacitor 93 is connected to the gate of a P-channel MOS transistor95 having its source connected to rail V_(DD) and having its drain nodeE connected to output CDN of the circuit. A zener diode 99 isforward-connected between rail V_(SS) and node D. Another edge detector,formed of a resistor 101 in series with a capacitor 103, is connectedbetween power supply rails V_(SS) and V_(DD). Node G between resistor101 and capacitor 103 is connected to the gate of an N-channel MOStransistor 105 having its source connected to rail V_(SS) and having itsdrain node H connected to output CDP of the circuit. A zener diode 109is reverse connected between rail V_(DD) and node G.

In normal operation, when the circuit is powered, nodes D and G arerespectively at high and low voltages, and transistors 95 and 105 arethus off. Thus, outputs CDN and CDP of the circuit are at highimpedance.

When the potential difference between rails V_(DD) and V_(SS) exceeds agiven threshold, diodes 99 and 109 become conductive in reverse mode byavalanche effect. This results in limiting the voltage of node D andcauses a rise of the voltage at node G. Transistors 95 and 105 thus turnon. Thus, outputs CDN and CDP of the circuit respectively switch to highand low states, that is, substantially to the voltages of rails V_(DD)and V_(SS).

When the integrated circuit is not powered, nodes D and G are at lowstates. If a fast positive overvoltage occurs between rails V_(DD) andV_(SS), node D remains in a low state, and node G rapidly switches to ahigh state, substantially corresponding to the voltage of rail V_(DD).Transistors 95 and 105 thus turn on and outputs CDN and CDP respectivelyswitch to high and low states.

An advantage of the detection and trigger circuit of FIG. 8 over thecircuit of FIG. 7 is that in the circuit of FIG. 8, in case of anovervoltage, outputs CDP and CDN are at voltages which are respectivelylower and higher than in the case of the circuit of FIG. 7. This resultsin a better conduction of transistors 31 and 33 and thus in a betterefficiency of the protection.

FIG. 9 shows another alternative embodiment of the protection structureof FIG. 5. The circuit of FIG. 9 is similar by many points to thecircuit of FIG. 6, and the features which are not necessary to highlightthe advantages of this circuit will not be described again hereafter.

In the circuit of FIG. 9, detection and trigger circuit 77 of FIG. 6 isreplaced with a detection and trigger circuit 117 comprising, inaddition to outputs CDP and CDN respectively connected to the gates oftransistors 31 and 33, outputs CDP2 and CDN2.

As in the circuit of FIG. 6, NAND gate 41 is connected to power supplyrail V_(DD) via a P-channel MOS transistor 61. An edge detectorcomprising a capacitor 63 in series with a resistor 65 is connectedbetween rails V_(DD) and V_(SS). The node between capacitor 63 andresistor 65 is connected to the gate of transistor 61. Similarly, NORgate 43 is connected to power supply rail V_(SS) via an N-channel MOStransistor 67. Another edge detector comprising a capacitor 69 in serieswith a resistor 71 is connected between rails V_(SS) and V_(DD). Thenode between capacitor 69 and resistor 71 is connected to the gate oftransistor 67.

The circuit of FIG. 9 further comprises a P-channel MOS transistor 111having its source connected to rail V_(DD) and having its drainconnected to the gate of transistor 61. The gate of transistor 111 isconnected to output CDP2 of detection and trigger circuit 117. Thecircuit of FIG. 9 also comprises an N-channel MOS transistor 113 havingits source connected to rail V_(SS) and having its drain connected tothe gate of transistor 67. The gate of transistor 113 is connected tooutput CDN2 of circuit 117.

In normal operation, signals CDP and CDN are at high impedance, andsignals CDP2 and CDN2 respectively are at high and low states,maintaining transistors 111 and 113 off. Nodes A and B respectively areat low and high states, maintaining transistors 61 and 67 on. Thus, theamplification stage control circuit is powered and, due to the highimpedance of outputs CDP and CDN, its normal operation is not disturbed.

In case of a positive overvoltage between rails V_(DD) and V_(SS),signals CDP and CDN respectively switch to low and high states, whichcauses the simultaneous turning-on of transistors 31 and 33 and theremoval of the overvoltage.

As in the circuit of FIG. 6, the coupling of the power supplies of NANDgate 41 and NOR gate 43 with edge detectors is an additional way ofascertaining the turning-on of transistors 31 and 33 when a fastpositive overvoltage occurs between rails V_(DD) and V_(SS) while theintegrated circuit is not powered.

The provision of transistors 111 and 113 also enables to ascertain thecutting-off of the power supply of gates 41 and 43 when a slow positiveovervoltage occurs between rails V_(DD) and V_(SS). When a positiveovervoltage occurs between rails V_(DD) and V_(SS), outputs CDP2 andCDN2 of circuit 117 respectively switch to low and high states, whichturns on transistors 111 and 113. This results in a rise of the gatevoltage of transistor 61 and a drop of the gate voltage of transistor67, which turns off transistors 61 and 67. NAND gate 41 and NOR gate 43are thus not powered and their respective outputs are floating, atundetermined states. Detection and trigger circuit 117 can thus freelycontrol the turning-on of protection transistors 31 and 33 via itsoutputs CDP and CDN.

FIG. 10 shows an embodiment of detection and trigger circuit 117 of theprotection structure of FIG. 9. The circuit of FIG. 10 comprises all theelements of the circuit of FIG. 7 and further comprises zener diodes 121and 123 respectively forward-connected between output CDN2 and railV_(DD), and reverse-connected between output CDP2 of the circuit andrail V_(SS), as well as resistors 125 and 127 respectively connectedbetween output CDN2 and rail V_(SS) and between output CDP2 and railV_(DD).

In normal operation, when the circuit is powered, diodes 81, 83, 121,and 123 are non-conductive. Thus, outputs CDN and CDP are at highimpedance and outputs CDN2 and CDP2 respectively are at low and highstates.

When the voltage difference between rails V_(DD) and V_(SS) exceeds agiven threshold, diodes 81, 83, 121, and 123 become conductive inreverse mode, by avalanche effect. Thus, outputs CDN and CDN2 switch toa high state, that is, substantially to the same voltage as rail V_(DD)minus a value V_(Z) corresponding to the threshold voltage of thediodes. Further, outputs CDP and CDP2 switch to a low state, that is,substantially to voltage V_(Z) corresponding to the threshold voltage ofthe diodes.

FIG. 11 shows a preferred alternative embodiment of detection andtrigger circuit 117 of the protection structure of FIG. 9. The circuitof FIG. 11 shows all the elements of the circuit of FIG. 8. Only theadditional elements will be described herein. Node D is connected to thegate of a P-channel MOS transistor 131 having its source connected torail V_(DD) and having its drain node connected to output CDN2 of thecircuit. A resistor 133 is connected between output CDN2 and railV_(SS). Further, node G is connected to the gate of an N-channel MOStransistor 135 having its source connected to rail V_(SS) and having itsdrain node connected to output CDP2 of the circuit. A resistor 137 isconnected between output CDP2 and rail V_(DD).

In normal operation, when the circuit is powered, nodes D and G arerespectively at high and low voltages, maintaining transistors 95, 131,105, and 135 off. Thus, outputs CDN and CDP of the circuit are at highimpedance and outputs CDN2 and CDP2 respectively are at low and highstates.

When the potential difference between rails V_(DD) and V_(SS) exceeds agiven threshold, diodes 99 and 109 become conductive in reverse mode, byavalanche effect. This limits the voltage of node D and causes a rise ofthe voltage at node G. Transistors 95, 131, 105, and 135 thus becomeconductive. Thus, outputs CDN and CDN2 switch to a high state, that is,substantially to the voltage of rail V_(DD), and outputs CDP and CDP2switch to a low state, that is, substantially to the voltage of railV_(SS).

When the integrated circuit is not powered, nodes D and G are at lowstates. If a fast positive overvoltage occurs between rails V_(DD) andV_(SS), node D remains in a low state, and node G rapidly rises to ahigh state, substantially corresponding to the voltage of rail V_(DD).Transistors 95, 131, 105, and 135 thus turn on. Outputs CDN and CDN2switch to a high state and outputs CDP and CDP2 switch to a low state.

An advantage of the provided embodiments is that they enable, in anintegrated circuit, to decrease the silicon surface area specificallydedicated to the protection against electrostatic discharges.

Eliminating the MOS transistors specifically dedicated to the protectionenables to decrease the electric overconsumption linked to leakagecurrents through these transistors.

Specific embodiments of the present invention have been described.Different variations and modifications will occur to those skilled inthe art. In particular, embodiments of detection and trigger circuitshave been described in relation with FIGS. 7 and 8. The presentinvention is not limited to these specific cases. It will be within theabilities of those skilled in the art to use any other circuit capableof detecting positive overvoltages between rails V_(DD) and V_(SS) andto accordingly control the gates of the transistors of the outputamplification stage.

Further, the present invention is not limited to the use of the circuitdescribed in relation with FIG. 4, to control, in normal operation, theturning-off and the turning-on of the MOS transistors of the outputamplification stage.

Similarly, other logic blocks than those described in relation withFIGS. 6 and 9 may be provided to interrupt, in case of an overvoltage,the normal power supply of the circuit for controlling the transistorsof the output amplification stage.

Such alterations, modifications, and improvements are intended to bepart of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

What is claimed is:
 1. An integrated circuit protected againstelectrostatic discharges, having output pads coupled to amplificationstages, each stage comprising, between first and second power supplyrails, a P-channel MOS power transistor in series with an N-channel MOSpower transistor, this integrated circuit further comprising protectionmeans for simultaneously turning-on the two transistors when a positiveovervoltage occurs between the first and second power supply rails, saidprotection means comprising a detection and trigger circuit comprising:a first edge detector comprising a resistor in series with a capacitor,connected between the first and second rails; a second edge detectorcomprising a resistor in series with a capacitor, connected between thesecond and first rails; a P-channel MOS transistor having its source andits drain respectively connected to the first rail and to a firstoutput, and having its gate connected between the resistor and thecapacitor of the first edge detector; an N-channel MOS transistor havingits source and its drain respectively connected to a second rail and toa second output, and having its gate connected between the resistor andthe capacitor of the second edge detector; and first and second zenerdiodes respectively forward-connected between the second rail and thegate of the P-channel transistor, and between the gate of the N-channeltransistor and the first rail.
 2. The integrated circuit of claim 1,wherein in each amplification stage, the sources of the P-channel andN-channel power transistors are respectively connected to the first andsecond power supply rails, and the drains of the power transistors areconnected to the output pad.
 3. The integrated circuit of claim 1,comprising a control circuit for each amplification stage to control, innormal operation, the turning-off and the turning-on of the powertransistors, this control circuit comprising at least one outputconnected to the gates of the power transistors, and wherein saidprotection means comprise: first and second resistors respectivelyconnected between said at least one output of the control circuit andthe respective gates of the P-channel and N-channel power transistors.4. The integrated circuit of claim 3, wherein the amplification stagecontrol circuit is connected to the first and second power supply railsvia P-channel and N-channel MOS transistors, having their respectivegates connected to edge detectors capable of controlling the turning offof these transistors when a positive overvoltage occurs between thefirst and second power supply rails.